The disclosed subject matter relates generally to integrated circuits and, more particularly, to a device having bias temperature instability test structures and a system for measuring the test structures.
Bias Temperature Instability (BTI) is an issue in deep submicron technologies. BTI affects devices which are kept in an active state for extended periods of time. For example, a custom array, or any domino circuit, often requires a keeper to hold the voltage on pre-charged bitlines if none of the pull-down transistors fire. To be properly sized, the keeper should be large enough to compensate the pull down leakage under worst process corners and noise considerations and should also be small enough to ensure fast evaluation when pull-down transistors do fire. However, negative bias temperature instability (NBTI) effectively weakens the keeper PFET over time. Positive bias temperature instability (PBTI) also has the potential to weaken pull-down NFETs over time.
Current testing methodology for determining the effects of BTI requires the use of automated die stepping on individual devices. This testing technique may require long periods of time to generate data for a single test condition. Also, automated test equipment requires significant capital expenditures. Hence, the available testing resources may be limited, further increasing the potential for delay in ascertaining BTI test results.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.